One type of prior non-volatile semiconductor memory is the flash electrically erasable programmable read-only memory ("flash EEPROM"). The flash EEPROM can be programmed by a user, and once programmed, the flash EEPROM retains its data until erased. After erasure, the flash EEPROM may be programmed with new code or data.
Flash memories differ from conventional electrically erasable programmable read only memory ("EEPROMs") with respect to erasure. Conventional EEPROMs typically use a select transistor for individual byte erase control. Flash memories, on the other hand, typically achieve much higher density with single transistor cells.
For one prior flash EEPROM, a logical "one" means that few if any electrons are stored on a floating gate associated with a bit cell. A logical "zero" means that many electrons are stored on the floating gate associated with the bit cell. Erasure of prior flash memory devices causes a logical one to be stored in each bit cell. Each single bit cell of a flash memory cannot be overwritten from a logical zero to a logical one without a prior erasure. Each single bit cell of that flash memory can, however, be overwritten from a logical one to a logical zero, given that this entails simply adding electrons to a floating gate that contains the intrinsic number of electrons associated with the erased state.
Due to the nature and design of a typical flash memory device, the entire device must be erased in order to erase any one cell in that device. This exposes the data in the memory device to potential data loss or corruption due to the erasure and reprogramming process whenever a portion of the data needs to be erased and reprogrammed.
One type of flash memory includes array blocking. Flash memory array blocking allows segregating different portions or types of data. In this way, when one portion needs to be erased, the other portion(s) do not have to be erased and are therefore not exposed to potential data loss or corruption. Thus, flash memory array blocking provides an increased level of data integrity previously achieved through the use of multiple chips each containing a different portion or type of data.
One prior flash EEPROM is the 28F256 complementary metal oxide semiconductor ("CMOS") flash memory sold by Intel Corporation of Santa Clara, Calif., which is a 256 kilobit flash EEPROM. The 28F256 flash memory includes a command register to manage electrical erasure and reprogramming. Commands are written to the command register from a controlling microprocessor using standard microprocessor write timings. The command register contents serve as input to an internal state machine that controls erase and programming circuitry.
The controlling microprocessor controls the erasure and programming of the flash memory. A prior Quick-Erase.TM. algorithm of Intel Corporation can be used by the microprocessor to erase the flash memory. The prior Quick-Erase.TM. algorithm requires that all bits first be programmed to their charged state, which is data equal to 00 (hexidecimal). Erasure then proceeds by pulling the source of the transistors in the array up to a high voltage level for a period of 10 msec, while keeping the transistor gates at zero volts. After each erase operation, byte verification is performed. The prior Quick-Erase.TM. algorithm allows up to 3000 erase operations per byte to recognize erasure failure. Proper device operation requires that the erasure procedure be strictly followed.
The prior Quick-Pulse Programming.TM. algorithm of Intel Corporation can be used by the microprocessor to then program the flash memory. The Quick-Pulse Programming.TM. algorithm requires that a programming pulse of a specific duration and voltage level be applied to the gate and drain of the selected transistors in the array. For example, for certain prior Intel flash memories a programming pulse of 10 .mu.sec has been suggested while Vpp is held at 12.75. After the programming pulse is applied, the user must verify whether the memory cell addressed is properly programmed. If not properly programmed, a programming pulse may be reapplied a number of times before a programming error is recognized. Intel's Quick-Pulse Programming.TM. algorithm allows up to 25 programming operations per byte. Proper and reliable operation of the flash memory mandates that the programming procedure be strictly followed.
One disadvantage of the prior way of using a microprocessor to control erasure and programming of the flash memory is that it ties up the microprocessor, thus requiring a relatively high level of microprocessor overhead. This, in turn, decreases system throughput.
Another disadvantage of the prior way of using a controlling microprocessor to control the erasure and programming of the flash memory is the relatively high complexity of typical erasure/programming software. This complex software requires a relatively high level of user sophistication. Moreover, this complex software increases the likelihood of a customer error, such as over-erasure of the flash memory.
One disadvantage of prior flash memories is that certain portions of data could not be selectively protected from accidental erasure or programming.